Title:
MULTIPROCESSOR PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPH01311358
Kind Code:
A
Abstract:
PURPOSE:To prevent the processing capacity of the whole system from being dropped by providing a test-and-set (TAS) instruction with a waiting time so that the TAS instruction is not continuously executed at a short time interval. CONSTITUTION:A waiting time W is previously set up in a space area of the TAS instruction. The gate word of a memory area to be accessed is checked, and when its contents are '0', the value is substituted to '1', a state indicator is set up to '0' and then processing is transferred to the succeeding instruction. When the contents of the gate word is '1', the instruction is waited by the waiting time W set up in the operand of the TAS instruction to suspend the processing, and after setting up '1' to the state indicator, the processing is transferred to the succeeding instruction. Consequently, the TAS instruction is not concentrically and continuously repeated until a clock in a main memory 5 is released, so that the processing capacity of the system can be prevented from being dropped due to frequent access to a system bus 1.
Inventors:
TAKEUCHI YOSHIHIKO
Application Number:
JP14205088A
Publication Date:
December 15, 1989
Filing Date:
June 09, 1988
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06F15/16; G06F9/52; G06F12/00; G06F15/177; (IPC1-7): G06F12/00; G06F15/16
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)