To provide a system for supplying synchronizing clock to a CPU with low skew.

This multiprocessor synchronizing system synchronizes a plurality of CPU boards 30a to 30d. In this system, a synchronizing message transmitter 10 transmits a synchronizing message to each of the plurality of CPU board 30a to 30d and the synchronizing message is transmitted via switches 20a to 20c. The CPU boards 30a to 30d have clock control registers for controlling time and synchronizing control mechanisms 40a to 40d for receiving the synchronizing message including a synchronizing command for controlling synchronization of the plurality of CPU boards 30a to 30d and controlling the clock control registers by using the synchronizing command contained in the received synchronizing message. Switches 20a to 20c are arranged between the synchronizing message transmitter 10 and each of the plurality of CPU boards 30a to 30d so that the number of the switches 20a to 20c may be equal. As a result, the transmission of the synchronizing message with low skew is realized.