Title:
MULTIPROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JP2003330901
Kind Code:
A
Abstract:
To process data or the like at high speeds without bringing a processor into a wait state even if access contention occurs.
This multiprocessor system is provided with two processors, and a dual-port memory accessible from the two processors. The system is equipped with a dual-port memory control device functioning so as not to bring the processors into a wait state in access contention. The dual-port memory control device can adjust access timing and is equipped with a FIFO memory.
Inventors:
MATONO MASAO
Application Number:
JP2002140978A
Publication Date:
November 21, 2003
Filing Date:
May 16, 2002
Export Citation:
Assignee:
YASKAWA ELECTRIC CORP
International Classes:
G06F15/167; G06F12/00; G06F13/376; G06F15/177; (IPC1-7): G06F15/167; G06F12/00; G06F13/376; G06F15/177