Title:
MULTIPROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JP2004127163
Kind Code:
A
Abstract:
To provide a multiprocessor system capable of properly preventing unauthorized acceptance with a simple hardware structure.
A comparator 30 and a mask register 31 are added between a priority determination part 23 and output parts 241, 242. When a processor 21 accepts an intercepting signal T1, the processor 21 starts execution of interception processing routine and changes a value of the mask register 31 to the maximum (a value of highest priority). Thereby, the interrupt signal U is canceled. Or an interrupt flag signal Ua and an interrupt level signal Ub are cleared. Accordingly, the interrupt signals T1, T2 are also cleared.
Inventors:
SAKUKAWA MAMORU
Application Number:
JP2002293595A
Publication Date:
April 22, 2004
Filing Date:
October 07, 2002
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
G06F15/177; G06F9/46; G06F9/48; G06F13/26; (IPC1-7): G06F9/46; G06F15/177
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita
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