Title:
MULTIPROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPS60151775
Kind Code:
A
Abstract:
PURPOSE:To reduce burden of software and make synchronization accurately by starting a program cycle by a clock signal from a clock device commanded by one of plural processors. CONSTITUTION:Start stop control and setting control of period of generation of clock signals CL of a clock device 9 are made by a master CPU1. Period of the clock signals CL is set to a period longer to some degree than any of program cycles of the master CPU1 and slave CPU2-3. The clock signals CL are inputted to each CPU as interruption signals. Each CPU starts its own program processing simultaneously with inputting of the clock signal CL, and when its own program cycle is finished, makes idling operation, and when next clock signal CL is inputted, starts processing of own next program again.
Inventors:
YAMAMOTO YUTAKA
Application Number:
JP799584A
Publication Date:
August 09, 1985
Filing Date:
January 19, 1984
Export Citation:
Assignee:
CHIYUUSHIYOU KIGIYOU SHINKOU J
International Classes:
G05B15/02; G05B19/18; G05B19/414; G06F9/52; G06F15/16; G06F15/17; G06F15/177; (IPC1-7): G05B15/02; G05B19/42; G06F15/16
Domestic Patent References:
| JPS4998146A | 1974-09-17 | |||
| JPS56162168A | 1981-12-12 |
Attorney, Agent or Firm:
Takeo Honjo