To provide a multiprocessor capable of rearranging contexts and performing context switching without stopping arithmetic processing of a processor.

A spill/fill cache register accesses a cache memory by using an internal bus of a different system and performs data rearrangement processing in parallel with arithmetic processing of the processor element so as to make the number of pieces of data stored in a register file within the range between an upper limit and a lower limit while all of a plurality of processor units except the register itself and its own processor element do not access the cache memory. A context switch controller switches a context corresponding to an unswitched thread to a context corresponding to a switched thread when the processor element switches threads on the basis of a value of a context pointer held by a context pointer register.