PURPOSE: To provide a gate array, in which a development cost can be reduced, by removing factors of connection mistake, when a plurality of users constitute a circuit in time same chip.
CONSTITUTION: When I/O buffer part 1, basic cell part 2, selector, and buffer block number and input/output terminal are assigned and provided and each user builds said parts as far as selector into a circuit and performs design, a plurality(N) of users can constitute the circuit in the same chip easily and without making a mistake. Also, when the I/O buffer with function preselection capability is prepared, a user can be provided with the gate array without the development of a new substrate mask and the state of the circuit in the gate array can be grasped so that a system bag is facilitated.
MATSUO OSAMU
JPS59111343A | 1984-06-27 | |||
JPS59122234A | 1984-07-14 |
Next Patent: METHOD OF QUENCHING IN DRY COKE QUENCHING FACILITY