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Patent Searching and Data


Title:
MULTIUSER GATE ARRAY
Document Type and Number:
Japanese Patent JPH06310689
Kind Code:
A
Abstract:

PURPOSE: To provide a gate array, in which a development cost can be reduced, by removing factors of connection mistake, when a plurality of users constitute a circuit in time same chip.

CONSTITUTION: When I/O buffer part 1, basic cell part 2, selector, and buffer block number and input/output terminal are assigned and provided and each user builds said parts as far as selector into a circuit and performs design, a plurality(N) of users can constitute the circuit in the same chip easily and without making a mistake. Also, when the I/O buffer with function preselection capability is prepared, a user can be provided with the gate array without the development of a new substrate mask and the state of the circuit in the gate array can be grasped so that a system bag is facilitated.


Inventors:
MIHASHI KAORU
MATSUO OSAMU
Application Number:
JP9637393A
Publication Date:
November 04, 1994
Filing Date:
April 23, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/118; H01L21/82; (IPC1-7): H01L27/118; H01L21/82
Domestic Patent References:
JPS59111343A1984-06-27
JPS59122234A1984-07-14
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)