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Title:
MUTING CIRCUIT
Document Type and Number:
Japanese Patent JPS5634212
Kind Code:
A
Abstract:

PURPOSE: To eliminate pulse noise effectively, by supplying an input signal to one input terminal of a differential amplifier and by applying this output signal to the other terminal while controlling the output signal to a prescribed level to subject the output signal to AC negative feedback and by connecting a backward transistor in parallel to the negative feedback path.

CONSTITUTION: A muting circuit is constituted with the first differential amplifier A, the second differential amplfier B, bias circuit 10, and so on. The signal from input terminal 1 in the circuit consituted in this manner is amplified by transistors 2 and 3 of the first differential amplifier A, and simultaneously, the output signal is supplied to the base of transistor 3 and is subjected to negative feedback. Further, the output signal is applied to the base of one transistor 16 of the second differential amplifier B through the time constant circuit consisting of transistor 13, capacitor 14, and resistance 15, and the voltage of capacitor 9 is applied to the base of the other transistor 17, and the output signal generated in the collector of transistor 16 is applied to variable impedance 20 through transistor 19, thus subjecting the circuit to AGC.


Inventors:
ABE KOUJI
KUROSAWA NOBUYUKI
Application Number:
JP11063879A
Publication Date:
April 06, 1981
Filing Date:
August 30, 1979
Export Citation:
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Assignee:
SONY CORP
International Classes:
H03F1/00; H03G3/34; H04B1/10; (IPC1-7): H03F1/00; H03G3/34
Domestic Patent References:
JPH0585348B21993-12-07
JPS5310829A1978-01-31
JPS5317025A1978-02-16