N-ARY ANALOG ADDER - FUJITSU LTD

Title:

N-ARY ANALOG ADDER

Document Type and Number:

Japanese Patent JPH0476790

Kind Code:

A

Abstract:

PURPOSE: To increase a dynamic range by adding plural n-ary analog data, subtracting a saturation value from the added value in accordance with the saturated state of the added value to compute the least significant digit(LSD) and computing a carry signal corresponding to the saturated state of the added value.

CONSTITUTION: A 2nd analog circuit 2 adds plural n-ary analog data and subtracts a saturation value from the added value in accordance with a saturated state detected by the 1st analog circuit 1, so that the LSD of the added value of plural n-ary analog data can be computed. Since a 3rd analog circuit 3 outputs a carry signal corresponding to the saturated state detected by the 1st analog circuit 1, the carry of the added value of plural n-ary analog data can be computed. Consequently, the dynamic range can be increased.

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Inventors:

SATO SHINJI

Application Number:

JP19179790A

Publication Date:

March 11, 1992

Filing Date:

July 18, 1990

Export Citation:

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Assignee:

FUJITSU LTD

International Classes:

G06G7/14; (IPC1-7): G06G7/14

Attorney, Agent or Firm:

Teiichi Ijiba (2 outside)

Next Patent: JPS476791