Title:
NAND background-processing control device
Document Type and Number:
Japanese Patent JP6193189
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To advance NAND background processing by maximally utilizing a spare time when a real time task does not perform access to an NAND device.SOLUTION: An NAND background processing control device includes: a host device 10 having a real time OS 11 for periodically executing a real time task; and a memory device 20 configured so as to be communicable with the host device, which has an NAND type flash memory and a device side OS 21. The device side OS transmits a predicted execution time and the number of target blocks required for NAND background processing for performing garbage collection to a host side OS, and the host side OS transmits the execution start enabling time and execution enabling time of the NAND background processing for preventing real time task execution from being affected to the device side OS, and the device side OS executes the NAND background processing only for the execution enabling time at the execution start enabling time in a spare time when the real time task does not perform access to the memory device side.SELECTED DRAWING: Figure 4
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Inventors:
Nishino Rena
Hiroshi Nosue
Coral lopez daniel
Ryo Kobayashi
Yamada Shindai
Kodai Okamoto
Kazuhiro Hayashi
Akihiro Suzuki
Hiroshi Nosue
Coral lopez daniel
Ryo Kobayashi
Yamada Shindai
Kodai Okamoto
Kazuhiro Hayashi
Akihiro Suzuki
Application Number:
JP2014167517A
Publication Date:
September 06, 2017
Filing Date:
August 20, 2014
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F12/02; G06F12/00
Domestic Patent References:
| JP2002297443A | ||||
| JP2012185653A |
Foreign References:
| WO2010013445A1 |
Attorney, Agent or Firm:
Amagi International Patent Office
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