Title:
【発明の名称】ビルディングブロックの端子位置設定方法
Document Type and Number:
Japanese Patent JP2607501
Kind Code:
B2
Abstract:
PURPOSE:To shorten wiring length among blocks, and to reduced the area of a chip by assigning a terminal onto the side of a poly cell block, computing the superposition of the existing side of an aimed terminal and the existing range of a component parallel with the existing side of the aimed terminal of a wiring, to which the aimed terminal is connected, and determining the position of the aimed terminal within the range. CONSTITUTION:The positions of terminals for a building block system integrated circuit in which a plurality of circuit blocks including poly cell blocks are arranged to a semiconductor substrate are set. In such a case, the terminals are assigned on the sides of the poly cell block E, the superposition of the existing side of the aimed terminal 1 and the existing range of a component parallel with the existing side of said aimed terminal 1 of the wiring of a signal, to which the aimed terminal 1 is connected, is computed, and the position of the aimed terminal is determined within the range. Accordingly, the positions of the terminals are decided efficiently, thus allowing the shortening of wirings among the blocks and the reduction of wiring regions.
Inventors:
Murakoto Masako
Masaaki Yamada
Masaaki Yamada
Application Number:
JP3141287A
Publication Date:
May 07, 1997
Filing Date:
February 16, 1987
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/82; G06F17/50; H01L21/822; H01L27/04; H01L27/10; (IPC1-7): H01L21/82; G06F17/50; H01L21/822; H01L27/04
Domestic Patent References:
| JP5492190A | ||||
| JP60109247A |
Attorney, Agent or Firm:
Hideaki Tokawa (1 outside)