Title:
【発明の名称】アクティブマトリックスアレイの検査方法
Document Type and Number:
Japanese Patent JP2506840
Kind Code:
B2
Abstract:
PURPOSE: To easily detect a defect or a thin film transistor TFT by setting at least one of the drain terminal of the TFT and a picture element electrode and a gate signal line to the short-circuit state. CONSTITUTION: Connection means GSm to all gate signal lines are closed, and a voltage applying means 10 generates a signal to turn off TFTs. Next, a connection means SS1 to a source signal line is closed, and a voltage measuring means 11 measures the voltage between both ends of a pickup resistance R1 . In this case, no voltage is measured by the voltage measuring means if TFTs connected to the source signal line S1 are indefectible. When the connection means SS1 is opened and a connection means SS2 is closed, a negative voltage is measured by the voltage measuring means 11 because of a current path passing the resistance R2 , a short-circuit defect 6, a short-circuit part C32 , and G3 , and the occurrence of a source-drain short-circuit defect in TFTs connected to a source signal line S2 is detected. Thus, an active matrix array is quickly checked without contacting.
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Inventors:
TAKAHARA HIROSHI
Application Number:
JP28245387A
Publication Date:
June 12, 1996
Filing Date:
November 09, 1987
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R31/02; G02F1/13; G01R31/28; G02F1/133; G02F1/136; G02F1/1368; G09G3/36; H01L27/12; H01L29/786; (IPC1-7): G02F1/136; H01L29/786
Domestic Patent References:
| JP63167333A |
Attorney, Agent or Firm:
Tomoyuki Takimoto