Title:
SYNAPSE MOS TRANSISTOR
Document Type and Number:
Japanese Patent JPH0637312
Kind Code:
A
Abstract:
PURPOSE: To form a multiple synapse MOS transistor, wherein outside ratios of the gate are different by forming, at a single source electrode and a drain electrode, multiple gate electrodes wherein length or width, or, both length and with are different. CONSTITUTION: On a P-type substrate 100, an n<+> -well is formed, and then a source electrode 01 and a drain electrode 102 are formed. On the P-type substrate 100, an oxide film SiO2 104 is coated, and over the oxide film, six gate electrodes 103 whose width Ws are 1, 2, 4, 8, 16, and 32, while a distance L from the source electrode 101 to the drain electrode 102 being identical, are formed. With an NMOS structure, a synapse NMOS transistor is thus formed. The current flowing in each gate increases as width W increases. Each channel, formed with six gates, has different conductance, while the sum of six conductances becomes one conductance of the synapse NMOS transistor.
Inventors:
TEI KOUSEN
Application Number:
JP12385493A
Publication Date:
February 10, 1994
Filing Date:
May 26, 1993
Export Citation:
Assignee:
GOLD STAR ELECTRONICS
International Classes:
G06N3/063; H01L29/78; (IPC1-7): H01L29/784
Attorney, Agent or Firm:
Tadahiko Ito (1 outside)