PURPOSE: To increase a read-out speed by setting the precharge level of bit line at a level higher than a level at which pull-up N-type transistor is turned On only by changing a circuit without changing process stages and quickening the fall of bit line at the time of the read-out.

CONSTITUTION: This memory is provided with precharge N-type transistors Q1, Q2 precharging bit lines of a memory array and pull-up N-type transistors Q4, Q5 connected between bit line and a power supply. Then, precharge pulses P' whose high level is higher than the power supply voltage are supplied to gates of precharging N-type transistors or a voltage lower than the power supply voltage is supplied to gates of pull-up of N-type transistors.