PURPOSE: To reduce the destuff jitter of a restored clock of the receiver side by comparing the phase difference between the synchronizing and asynchronizing signals with the threshold value of a cycle signal.

CONSTITUTION: A clock phase comparator 7a compares the phase of a write clock and that of a read clock of an elastic store 3 and detects the difference of rise time between both clocks to output this detecting result as a signal (j). A digital phase comparator 8 compares the addresses with each other to synthesize a signal (i). A phase comparison result synthesizer 9a synthesizes the signals (j) and (i) together to obtain a timing difference signal (d). A comparator 12 compares the signal (d) with the output positive stuff threshold value signal (c) of a synchronizing signal generator 10. When the signal (d) is smaller than the signal (c), it is decided that a positive stuff request signal (f) sent from the comparator 12 has a positive stuff request. A synchronizing signal generator 11 produces a negative stuff request signal (g) regardless of the timing conditions of the store 3. In such a constitution, the destuff jitter of a restored clock of the receiver side can be reduced.