Title:
FORMATION OF RESIST PATTERN
Document Type and Number:
Japanese Patent JP3050965
Kind Code:
B2
Abstract:
PURPOSE: To obtain the method for forming a fine pattern which is finer than the optical resolution limit as to the formation of a pattern by a silylized two- layered resist method for the manufacture of a semiconductor device.
CONSTITUTION: The upper-layer resist 7 of two-layered resist is patterned and at least its side wall 11 is silylized and used as a mask for etching to pattern even the lower-layer resist 6.
Inventors:
Takeshi Uesugi
Application Number:
JP24936891A
Publication Date:
June 12, 2000
Filing Date:
September 27, 1991
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G03F7/26; G03F7/095; G03F7/38; G03F7/40; H01L21/027; H01L21/302; H01L21/3065; (IPC1-7): G03F7/26; G03F7/095; G03F7/38; H01L21/027; H01L21/3065
Domestic Patent References:
| JP1154053A |
Attorney, Agent or Firm:
Kenji Ohnishi