Title:
NETWORK SYNCHRONIZING CLOCK CONTROL SYSTEM AND METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3047967
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a network synchronizing clock control system and method in which increase in cost can be prevented by realizing a simple circuit constitution without using an expensive VCO for synchronizing a radio side clock with an ISDN line side clock.
SOLUTION: A radio side clock MCLK and an ISDN line side clock SCLK are frequency-divided into the same frequency clock MCLKD and SCLKD for synchronizing the radio side clock MCLK with the ISDN line side clock SCLK, and then phase comparison is made. The radio side clock is controlled when the phase of the radio side clock is shifted only by a certain value with respect to the ISDN line side clock as a reference, and a clock with higher frequency than that of the radio side clock is outputted instead of the radio side clock in a certain time for clock insertion. Or the radio side clock is stopped in a certain time for clock deletion so that the deviation of the phase of the radio side clock with respect to the ISDN line side clock can be corrected.
Inventors:
Tsukasa Adachi
Application Number:
JP20929097A
Publication Date:
June 05, 2000
Filing Date:
August 04, 1997
Export Citation:
Assignee:
NEC
International Classes:
H04L7/00; (IPC1-7): H04L7/00
Attorney, Agent or Firm:
Masaru Watanabe (3 outside)