Title:
PHASING SIMULATOR
Document Type and Number:
Japanese Patent JP3074603
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To accurately output a signal being delayed without any signal interruption when changing phasing.
SOLUTION: A specific signal being converted to a digital signal by an A/D converter 31 is stored in a memory 36 in the order of address and is read successively, and the difference in a reading address for a writing address is varied for varying the delay time of a signal. Also, a noise signal being outputted from a noise generator 41 by a DPS is subjected to over-sampling processing, is D/A-converted, and then is converted to an analog signal, an image component is eliminated from the signal by a low-pass filter 45 before being inputted to an orthogonal modulator 47, and a signal being outputted from a delay circuit 35 is subjected to phasing fluctuation and Doppler shift, a clock frequency for a D/A converter 43 is varied for varying the band of the noise signal and hence for causing the amount of phasing fluctuation and the amount of Doppler shift to fluctuate.
Inventors:
Takehide Goto
Makoto Fujii
Hiroshi Itahara
Makoto Fujii
Hiroshi Itahara
Application Number:
JP10348898A
Publication Date:
August 07, 2000
Filing Date:
March 30, 1998
Export Citation:
Assignee:
Anritsu Corporation
International Classes:
G01R29/00; G01R31/00; H04B3/04; H04B7/005; (IPC1-7): G01R31/00; G01R29/00; H04B3/04; H04B7/005
Domestic Patent References:
| JP1254026A | ||||
| JP5714228A | ||||
| JP8265187A | ||||
| JP5875315A | ||||
| JP61262313A | ||||
| JP62245717A |
Attorney, Agent or Firm:
Masashi Hayakawa