PURPOSE: To realize the normality confirmation circuit for the multiplexer circuit by which the normal state of the multiplexer is simply confirmed without processing output data.

CONSTITUTION: The normality confirmation circuit for a multiplexer circuit 1 confirming the normal state of the multiplexer circuit 1 outputting parallel data in plural bits inputted in a time slot having a 1st period to a multiplexed highway of serial data for each 2nd period being a plural number of multiple of the 1st period is provided with an adder circuit 2 receiving the parallel data and providing the output of logical sum for a time slot of a same time and with a comparator circuit 4 receiving an output of the multiplexer circuit outputted to a multiplexed highway and the output of the adder circuit and decrementing data in the same time slot as that of OR of parallel data represented in the output of the adder circuit for each 2nd period sequentially and providing the subtraction result for a succeeding time slot.