Title:
【発明の名称】デマルチプレクサ装置
Document Type and Number:
Japanese Patent JP2551985
Kind Code:
B2
Abstract:
A demultiplexer for demultiplexing a multiplexed input data signal into M output channels using M sequencer means clocked from an overlapping M phase system clock. The system clock operates at a frequency equal to the input data signal rate divided by M. Each sequencer means is clocked by a unique combination of the M phase system clock signals to select one data channel from the multiplexed input data signal. Since all sequencer means circuits are synchronized to the system clock, no variable delay lines are needed to align the timing between the circuit stages. A time delay latch is provided where needed in each sequencer means to enable all channels to output data concurrently. The demultiplexer includes a real-time data-framing capability to assure that the input data is correctly mapped to the proper output channels.
Inventors:
ROBAATO JERARUDO SUWAATSU
Application Number:
JP25745788A
Publication Date:
November 06, 1996
Filing Date:
October 14, 1988
Export Citation:
Assignee:
EI TEI ANDO TEI CORP
International Classes:
H04J3/04; H04J3/06; H04L7/033; (IPC1-7): H04J3/04
Attorney, Agent or Firm:
Hirofumi Mimata