PURPOSE: To provide a gate array integrated circuit which improve gate activity ratio and that permits the measurement of gate characteristics such as delay time, etc., when operational abnormality is generated in a function circuit.

CONSTITUTION: Based on the output from a UVROM cell 7, an input circuit 8 and a selector 9 change the connecting condition of a gate characteristic measuring circuit 5 and a main function circuit 1, and one of the circuits is electrically connected with test pads 2a and 2b. Thus, even when the number of the test pads is small, the main function circuit 1 and the character measuring circuit 5 are formed on a pellet and the gate activity ratio is improved. When operational abnormality is generated in the main function circuit 1, the gate characteristics are measured by using the gate characteristic measuring circuit 5.