Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3025476
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To detect the increase of circuit current due to abnormality in a circuit consisting of a MOS transistor with a lower threshold voltage(Vt) composing a semiconductor integrated circuit.
SOLUTION: An inspected circuit 230 is composed of an address buffers 231,..., and a timing generator 234 which are circuit blocks consisting of low voltage MOS transisters TLP, TLN. A test enable signal TE to indicate an inspection, a motion selection signal/OP to indicate a motion and block selection signals S11-S61 to select a desired circuit block are supplied. In the case of inspection, in order to supply either of the detection currents I11-I61 of each circuit block selected by turning any of block selection signals S11-S61 and the test enable signal TE into H to the inspection circuit, the inspection circuit is equipped with NMOS transisters THN11-THN61 and PMOS transisters THP 11-THP 61 which are high in voltage.
Inventors:
Kazuko Nishimura
Hironori Akamatsu
Akira Matsuzawa
Hironori Akamatsu
Akira Matsuzawa
Application Number:
JP9863298A
Publication Date:
March 27, 2000
Filing Date:
April 10, 1998
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F11/22; H01L21/66; H01L21/822; H01L27/04; G01R31/28; (IPC1-7): G01R31/28; H01L21/822; H01L27/04
Domestic Patent References:
| JP6334010A | ||||
| JP823277A |
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)