Title:
【発明の名称】PLL回路
Document Type and Number:
Japanese Patent JP3080007
Kind Code:
B2
Abstract:
A PLL circuit detects a locked state as keeping always constant the ratio of an input signal to a locked state detection reference value by automatically and continuously changing the locked state detection reference value even when the frequency of the input signal is changed. A division ratio of a frequency divider in the PLL circuit is changed in response to an external signal. An analog signal Vc which is output from a loop filter 3 is applied to a delay circuit 7. When the analog signal Vc rises, a delay time Td of the delay circuit 7 decreases. The locked state detection reference value varies according to the frequency of the signal f1.
Inventors:
Shigeru Kuhara
Application Number:
JP22658096A
Publication Date:
August 21, 2000
Filing Date:
August 28, 1996
Export Citation:
Assignee:
NEC
International Classes:
H03L7/095; H03L7/183; H04L7/033; H03L7/089; (IPC1-7): H03L7/095
Domestic Patent References:
| JP6424630A | ||||
| JP54130861A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)