Title:
MICROPROCESSOR AND COMPILER
Document Type and Number:
Japanese Patent JP3079090
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a microprocessor and a compiler which can quickly execute processing for a subroutine.
SOLUTION: When a subroutine retrieval instruction fetched from an instruction memory 39 by an IDB(instruction data buffer) 29 is decoded by a decoder 18, a processor 10 executes a return address storing operation (1) where the stored value of a PC(program counter) 15 is increased by an INC(incrementer) 16 and this increment result is stored in an LR(return register) 13 as a return address, a branch operation (2) where the head address of a subroutine that is included in the subroutine call instruction is stored in the PC 15, and a stack securing operation (3) which is prepared for the use after the stored value of an SP(stack pointer) 12 is added by '-4' by an adder 22 and then stored again in the SP 12 respectively. These three operations of the processor 10 are executed in parallel to each other in a single machine cycle.
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Inventors:
Hidekazu Takayama
Tetsuya Tanaka
Tetsuya Tanaka
Application Number:
JP34801298A
Publication Date:
August 21, 2000
Filing Date:
December 08, 1998
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F9/42; G06F9/45; (IPC1-7): G06F9/42; G06F9/45
Domestic Patent References:
| JP991150A | ||||
| JP8305581A | ||||
| JP60118933A | ||||
| JP1142943A | ||||
| JP8305569A | ||||
| JP3230223A |
Attorney, Agent or Firm:
Shiro Nakajima (1 person outside)