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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND COMPUTATION PROCESSING SYSTEM USING SAME
Document Type and Number:
Japanese Patent JPH0529333
Kind Code:
A
Abstract:

PURPOSE: To realize a high gain by a method wherein an emitter region for a bipolar transistor is constituted of the following: a first region in which the lattice of a semiconductor crystal is contracted; and a second region in which the lattice of the semiconductor crystal is not contracted.

CONSTITUTION: Phosphorus ions are implanted by using an ion implantation method; after that, germanium ions are implanted and annealed. At this time, a band gap is narrowed in an emitter region 12 due to a lattice contraction. However, impurity atoms whose covalent bond radius is larger than that of silicon atoms are added to an emitter region 11. As a result, a lattice strain is compensated, and the band gap is not narrowed due to the lattice contraction. As a result, a wide gap emitter such as a heterojunction is formed. Thereby, even when a base is made as a thin layer and a base concentration is made high in order to make the speed of a transistor high, it is possible to obtain a high current gain.


Inventors:
UCHINO TAKASHI
NANBA MITSUO
KOBAYASHI TAKASHI
NAKAMURA TORU
Application Number:
JP18436191A
Publication Date:
February 05, 1993
Filing Date:
July 24, 1991
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L27/14; H01L21/331; H01L27/15; H01L29/73; H01L29/737; (IPC1-7): H01L21/331; H01L27/14; H01L27/15; H01L29/73
Attorney, Agent or Firm:
Junnosuke Nakamura (1 outside)