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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0738352
Kind Code:
A
Abstract:

PURPOSE: To provide the semiconductor integrated circuit which can execute control of gain by preventing a return loss of an input and without deteriorating a mutual modulation distortion, at the time of strong input signal.

CONSTITUTION: With respect to a gate of a signal amplification MESFET 1, a source is grounded to a ground through a bypass capacitor 6, the gate is grounded to a ground through a resistance 7, and between a drain electrode and a source electrode, a drain of an active MESFET 8 to which a resistance 2 is connected in parallel is connected, and by a voltage applied to a source electrode of the active MESFET 8, control of gain is executed. At the time of strong input signal, in the case a control voltage of the gain is set so that the MESFET 1 operates in the vicinity of a threshold voltage, the gain of the MESFET 1 goes down, and also, the active MESFET 8 is turned on, an input side is terminated by a channel resistance of the active MESFET 8, and also, a part of the input signal is allowed to escape to a ground, by which an input return loss at the time of low gain and deterioration of a mutual modulation distortion can be prevented.


Inventors:
MOTOYOSHI KANAME
TARA KATSUJI
Application Number:
JP17582093A
Publication Date:
February 07, 1995
Filing Date:
July 16, 1993
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H03G3/10; (IPC1-7): H03G3/10
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)