Title:
ラツチアツプ保護回路付き集積回路
Document Type and Number:
Japanese Patent JP2528794
Kind Code:
B2
Abstract:
A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit connects a capacitor bias generator to the capacitor when a voltage on the substrate bias terminal is less than a sum of a reference potential and a threshold voltage of a first transistor in the electronic protection circuit. The electronic protection circuit disconnects the capacitive bias generator from the capacitor when a voltage on the substrate bias terminal is greater than the sum. During normal operation the electronic protection circuit does not load a supply voltage source or a substrate bias voltage source with current.
More Like This:
| JPS6199363 | SUBSTRATE-POTENTIAL GENERATING CIRCUIT |
| JP4158214 | Semiconductor integrated circuit |
| JPH07219656 | CONSTANT VOLTAGE CIRCUIT |
Inventors:
ウエルナー、ペクツエーク
ヨーゼフ、ウインネルル
ヨーゼフ、ウインネルル
Application Number:
JP23993487A
Publication Date:
August 28, 1996
Filing Date:
September 22, 1987
Export Citation:
Assignee:
シーメンス、アクチエンゲゼルシヤフト
International Classes:
G05F3/20; G11C11/407; H01L21/822; H01L21/8238; H01L21/8242; H01L27/04; H01L27/08; H01L27/092; H01L27/108; (IPC1-7): H01L21/8238; H01L21/822; H01L21/8242; H01L27/04; H01L27/092; H01L27/108
Attorney, Agent or Firm:
富村 潔