Title:
SIGNAL SELECTION CIRCUIT SELECTING MAXIMUM OR MINIMUM LEVEL SIGNAL
Document Type and Number:
Japanese Patent JP2570989
Kind Code:
B2
Abstract:
PURPOSE: To obtain a signal selection circuit exactly taking out a maximum or minimum signal.
CONSTITUTION: When a signal with high potential from an input terminal I 11 is impressed on an input terminal I 12, much current flows from the constant current of a constant current source C 11 in a transistor QN 11 and the same current as this current flows out to a node N 12 from the current output end of a current mirror circuit 11. The part up to the constant current of this current flows in a power source terminal VSS through a transistor MN 12 and the part exceeding the constant current is bypassed by a diode D 11. A diode 12 becomes an OFF state because the current flowing in the transistor QN 12 is less than the first constant current. The current bypassed by the diode D 11 joins the constant current and flows in the power source terminal VSS via the transistor 11. The input terminal I 11 and an output terminal U 11 becomes the same potential which is closer to the potential on the side of a first power source terminal than a common node N 11 by the only potential between a base and an emitter.
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Inventors:
KOGA HIROSHI
Application Number:
JP26448793A
Publication Date:
January 16, 1997
Filing Date:
October 22, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H04N5/14; H03D1/00; H03K17/00; (IPC1-7): H03K17/00; H03D1/00; H04N5/14
Domestic Patent References:
| JP3291571A |
Attorney, Agent or Firm:
Wakabayashi Tadashi