Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0745507
Kind Code:
A
Abstract:
PURPOSE: To prevent that the check pattern of a lithography alignment pattern or a lithography monitor pattern is not formed with high precision.
CONSTITUTION: When height difference exists in a circuit region, a check pattern 106A which is simultaneously formed in the lithography process for forming a wiring 106 forms a retainer 105 which is positioned at the middle height between the lowest part and the hightest part. Thereby the formation precision of a pattern for lithography is improved, and the precision of the lithography process can be improved.
Inventors:
YANAGISAWA MASAYUKI
Application Number:
JP19105293A
Publication Date:
February 14, 1995
Filing Date:
August 02, 1993
Export Citation:
Assignee:
NEC CORP
International Classes:
H01L21/027; (IPC1-7): H01L21/027
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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