Title:
MANUFACTURE OF SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH065817
Kind Code:
A
Abstract:
PURPOSE: To reduce interference noise between bit lines by electromagnetically shielding an entire surface and an upper surface of a sidewall between the bit lines with a conductive film.
CONSTITUTION: A second conductive film 6 is provided on an upper part and an entire sidewall of a bit line 3 formed on a silicon substrate 2 having a predetermined isolation region 1, a transistor through a first insulating film 4, a second insulating film (sidewall) 5, a predetermined data storage region (capacitor) consisting of a node electrode 7, a capacity insulating film 8, a plate electrode 9 is formed on its upper part, and metal wirings 10 connected to the film 6 and a predetermined lower layer region is then formed.
Inventors:
OKADA SHOZO
Application Number:
JP16054992A
Publication Date:
January 14, 1994
Filing Date:
June 19, 1992
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/76; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/76
Attorney, Agent or Firm:
Yoshihiro Morimoto
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