PURPOSE: To exclude a steady-state current of a 1st or a next stage logic element corresponding to an input of a TTL level or the like other than a power supply voltage and a ground potential as an external input signal.

CONSTITUTION: A power supply voltage from a low voltage generating circuit 3 is applied to an inverter comprising a P-channel MOS transistor(TR) 11 and an N-channel MOS TR 13. When an external input signal IN is set to a low level (0.8V), the P-channel MOS TR 11 is turned on and the N-channel MOS TR 13 is turned off when a difference between a gate level and a source level is less than a threshold voltage VTN, an output of the inverter goes to a high level in a pull-up circuit 4 accordingly, a P-channel MOS TR 41 is turned on via a MOS inverter 42 and an output signal OUT is outputted at a power supply voltage VDD level (5.0V).