Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP2509717
Kind Code:
B2
Abstract:
A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region (10) and a logic region (11) including MOS transistors. A first insulating film (23) and a first electrode layer (24) are formed on a semiconductor substrate (22). Only those portions of the first insulating film (23) and first electrode layer (24) which are located in the logic region (11) are removed, without removing those portions of the first insulating film (23) and first electrode layer (24) which are located in the non-volatile memory cell region (10). A sacrificial film (25) is deposited for insulation over the entire surface of the memory cell region (10) and logic region (11), and then a resist film (26) is coated on the sacrificial film (25). Subsequently, impurity ions are implanted into a desired channel region (27) located in the logic region (11). The resist film (26) and sacrificial film (25) are removed, and thereafter a second insulating film and a second electrode layer are formed.
Inventors:
SHINADA KAZUYOSHI
YOSHIDA MASAYUKI
MIZUTANI TAKAHIDE
HANADA NAOKI
YOSHIDA MASAYUKI
MIZUTANI TAKAHIDE
HANADA NAOKI
Application Number:
JP31515689A
Publication Date:
June 26, 1996
Filing Date:
December 06, 1989
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/82; H01L21/8234; H01L21/8247; H01L27/088; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/115
Attorney, Agent or Firm:
Noriyuki Noriyuki (1 person outside)