DMOS TRANSISTOR AND PREPARATION THEREOF

Title:

DMOS TRANSISTOR AND PREPARATION THEREOF

Document Type and Number:

Japanese Patent JPH0750412

Kind Code:

A

Abstract:

PURPOSE: To reduce continuity resistance in a P-body region and a channel region by forming a short channel near a groove and making the concentration of the body region high. CONSTITUTION: A short channel is formed by making the concentration of a dose of arsenic in a direction away from a groove on a P-body region 3 and in the lateral direction within a concentration P<+> -body region 7 higher than that of a dose which is implanted into a source expanded region 8 as compared with an N<+> -source region 5. An ion accelerating voltage is applied and a dose are implanted to the P-body region 3 and the surface having an impurity concentration of 5×10<17> to 2×10<18> /cm<3> and is doped to a depth of 1.0 to 2.0 μm, so as to be highly concentrated. Consequently, the continuity resistance of a transistor is reduced, and the performance is improved.

Inventors:

FUUIAN SHIIE
MAIKU EFU CHIYANGU
HAMUZA IRUMAZU

Application Number:

JP7165094A

Publication Date:

February 21, 1995

Filing Date:

March 15, 1994

Export Citation:

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Assignee:

SILICONIX INC

International Classes:

H01L21/336; H01L29/10; H01L29/78; H01L29/08; (IPC1-7): H01L29/78; H01L21/336

Attorney, Agent or Firm:

Yoichi Oshima (1 outside)

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