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Title:
DIGITAL AMPLIFIER
Document Type and Number:
Japanese Patent JPH0715248
Kind Code:
A
Abstract:

PURPOSE: To suppress distortion caused by difference in the response delay time of the respective switching elements of a BTL circuit at the digital amplifier for driving a speaker through the BTL circuit after a digital acoustic signal whose pulse code is modulated is converted into pulse duration modulation.

CONSTITUTION: In the case of performing analog acoustic reproduction from a speaker 38 by amplifying the pulse code modulated acoustic signal from a compact disk device 27 or the like at a power amplifier 35 including a pair of complementary connected FET TR1 and TR2 or TR3 and TR4 after the signal is converted into the pulse duration modulation at a converter 31, the data converted by the converter 31 are corrected corresponding to the response delay time of the FET in a correction part 41. Thus, the generation of distortion caused by the difference of response delay time can be suppressed. Further, the converter 31 can be also shared for a specification change due to the change of the FET or the speaker 38, thereby cost can be reduced.


Inventors:
FUJIMOTO SHOJI
YAMATO TOSHITAKA
SAKO KAZUYA
Application Number:
JP15085093A
Publication Date:
January 17, 1995
Filing Date:
June 22, 1993
Export Citation:
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Assignee:
FUJITSU TEN LTD
International Classes:
H03F3/26; (IPC1-7): H03F3/26
Attorney, Agent or Firm:
Nishikyo Keiichiro



 
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