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Patent Searching and Data


Title:
FORMATION OF MULTILAYER INTERCONNECTION OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0714832
Kind Code:
A
Abstract:

PURPOSE: To provide a method of forming the multilayer interconnection of a semiconductor device, which is capable of preventing reliably a short-circuit between an upper metal wiring and a lower metal wiring using layer insulating films of a small film thickness.

CONSTITUTION: A first layer metal wiring 1 is formed between fellow silicon nitride films 11 formed on a semiconductor substrate S and thereafter, a first lower layer insulating film 2a and a first upper layer insulating film 2b are deposited in order. Then, after second layer contact holes 4 are formed in a first layer insulating film 2, grooves 12 for second layer metal wiring for embedding are formed in the film 2b and after that, a second layer metal wiring 5 is formed in the holes 4 and the grooves 12. Then, after a second lower layer insulating film 6a and a second upper layer insulating film 6b are deposited in order on the film 2b and the wiring 5, third layer contact holes 7 are formed in a second layer insulating film 6. Then, after a groove 13 for third layer metal wiring burying is formed in the film 6b, a third layer metal wiring 8 is formed.


Inventors:
TANPO TOSHIHARU
Application Number:
JP14352893A
Publication Date:
January 17, 1995
Filing Date:
June 15, 1993
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L21/302; H01L21/3065; H01L21/3205; H01L21/768; H01L23/522; (IPC1-7): H01L21/3205; H01L21/3065; H01L21/768
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)