Title:
【発明の名称】遅延型フリップフロップ回路
Document Type and Number:
Japanese Patent JP3011595
Kind Code:
B2
Abstract:
PURPOSE:To provide a delay type flip-flop D-FF circuit which excells in the high speed operability and can be integrated in a high degree by using four double input NOR gates, an inverter, and a depressiong type field effect transistor D-FET. CONSTITUTION:The dual input OR gates 31 and 32 are connected in an X-shape between a clock input terminal 20 and the nodes N11 and N12, and the dual input OR gates 33 and 34 are connected in an X-shaped between the nodes N11 and N12 and the output terminals 22 and 23 respectively. The input terminal of an inverter 41 is connected to a data input terminal 21, and the output terminal of the inverter 41 is connected to the drain of a D-FET 42 of an N channel. The gate of the D-FET 42 is grounded, and the source of the D-EFT 42 is connected to the node N12. When a clock CK rises or falls, the current is supplied or taken in between the output side of the inverter 41 and the node N12 via the D-FET 42. Thus the state of the node N12 is decided.
Inventors:
Hiroyuki Yamada
Shohei Seki
Yasushi Kawakami
Shohei Seki
Yasushi Kawakami
Application Number:
JP61994A
Publication Date:
February 21, 2000
Filing Date:
January 07, 1994
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H03K3/356; (IPC1-7): H03K3/356
Domestic Patent References:
| JP5392655A | ||||
| JP62258514A |
Attorney, Agent or Firm:
Yasunari Kakimoto