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Title:
PEDESTAL LEVEL ADDING DEVICE
Document Type and Number:
Japanese Patent JPH0630299
Kind Code:
A
Abstract:

PURPOSE: To improve accuracy for adding pedestal level data to a video signal being one of digital processing in the case of digitally processing the video signal in an NTSC system or the like.

CONSTITUTION: After pedestal level clamp processing at a clamp circuit 32, an analog video signal 31 is converted into a digital signal by an A/D conversion circuit 33. A pedestal level extraction circuit 1 extracts only the pedestal level data from the output of this A/D conversion circuit 33. Even when the A/D converted output is fluctuated, these extracted data follows up the fluctuation. Therefore, when these extracted data are added to the video signal after digital processing at a digital processing part 34 similar to the conventional one by a pedestal level adding circuit 36 similar to the conventional configuration, exact pedestal level addition can be provided.


Inventors:
SHIMURA KENJI
Application Number:
JP17965792A
Publication Date:
February 04, 1994
Filing Date:
July 07, 1992
Export Citation:
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Assignee:
FUJITSU GENERAL LTD
International Classes:
H04N5/16; (IPC1-7): H04N5/16
Domestic Patent References:
JPS62176380A1987-08-03
JPH02119468A1990-05-07



 
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