Title:
SYNCHRONIZATION PATTERN DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPH0541034
Kind Code:
A
Abstract:
PURPOSE:To securely detect a synchronization pattern for the purpose of promoting the recording density of a recording medium and the data transfer rate even when the period of a clock signal is shortened. CONSTITUTION:A shift register 11 (48 bits) for series/parallel-converting a regenerative signal obtained from a recording medium based on a clock signal, 1st decoders 12a, 12b and 12c for identifying individual symbol patterns A, B and C constituting the synchronization pattern and a majority deciding circuit 13 for comparing an identified number of the above symbol patters with a threshold and generating a detecting signal for showing the detection of the synchronization pattern are connected up in due order. Flip-flop circuits 14, 16, 18 and 20 (12 bits, 2 bits and 3 bits) are provided in this majority deciding circuit 13 in each position for deciding each operating result to be generated in turn within one period of the clock signal respectively.
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Inventors:
FUJIWARA TSUNEO
YAMAGUCHI TAKESHI
YAMAGUCHI TAKESHI
Application Number:
JP19435091A
Publication Date:
February 19, 1993
Filing Date:
August 02, 1991
Export Citation:
Assignee:
SHARP KK
International Classes:
G11B20/10; (IPC1-7): G11B20/10
Attorney, Agent or Firm:
Kenzo Hara
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