Title:
【発明の名称】レイアウトの検証方法およびその装置
Document Type and Number:
Japanese Patent JP3079936
Kind Code:
B2
Abstract:
PURPOSE: To verify a masking pattern for correcting a pseudo design rule error by outputting a rectangle before being divided by a cut line which generates a spacing error and the position of the rectangle. CONSTITUTION: The masking pattern constituted of the rectangles is constituted of the wirings LH1-LH3 and LV2 of a first wiring layer, the wirings LV1 and LV3 of a second wiring layer and the contacts VIA1 and VIA2 of the first wiring layer and the second wiring layer. The cut lines or slits for dividing the rectangle along the horizontal or vertical direction of the rectangle extended for minimum spacing or all the rectangles for which a spacing rule is defined are set in a masking layout constituted of the rectangles. Then, whether or not a distance between the adjacent rectangles present between the adjacent cut lines keeps a design rule is checked. Then, the rectangle before being divided by the cut line which generates the spacing error and the position of the rectangle are outputted.
Inventors:
Koichi Sato
Application Number:
JP3682395A
Publication Date:
August 21, 2000
Filing Date:
February 24, 1995
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP6349943A | ||||
| JP6223132A | ||||
| JP5249650A | ||||
| JP4111448A | ||||
| JP1287780A |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)