Title:
PROCESSOR PROVIDED WITH SPECULATIVE EXECUTION CONTROL FUNCTION
Document Type and Number:
Japanese Patent JP3037863
Kind Code:
B2
Abstract:
PURPOSE: To avoid the execution of a wasteful processing accompanying speculative execution of a conditional branch instruction.
CONSTITUTION: In an instruction execution mechanism 4, a comparison instruction preceding the conditional branch instruction, and a memory reference instruction immediately before the instruction are executed. When a cache error occurs and a pipeline is held as a result of that data designated by the effective address of the memory reference instruction is to be referred to, an instruction analysis mechanism 3 is notified of that from the instruction execution mechanism 4 through a route 41. Then, the instruction analysis mechanism 3 waits for a compared result acquirement notice accompanying the execution of the comparison instruction from the instruction execution mechanism 4 without executing the speculative analysis of the conditional branch instruction next to the comparison instruction becoming an analysis object at that time. When the notice is received, the branching of the conditional branch instruction is definitely judged based on the compared result, an instruction read mechanism 1 is notified of the judged result through a route 31 and instruction fetch is requested.
Inventors:
Nobuhiko Yamagami
Yasumasa Nakata
Yasumasa Nakata
Application Number:
JP33685093A
Publication Date:
May 08, 2000
Filing Date:
December 28, 1993
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F9/38; (IPC1-7): G06F9/38
Domestic Patent References:
| JP4200722A | ||||
| JP6431228A | ||||
| JP57150039A | ||||
| JP3113535A | ||||
| JP6457338A | ||||
| JP2242338A | ||||
| JP63148329A |
Attorney, Agent or Firm:
Takehiko Suzue