PURPOSE: To reduce terminal capacity in a memory card and to reduce the operation current of the memory card by dividing the address line of the memory card to plural blocks with a logic circuit and connecting them to a memory.

CONSTITUTION: A card address 2 from a connector 1 is supplied to the input buffer 8 of the logic circuit 5, and the output is divided into two blocks and supplied to the output buffers 9, 10. The output of the buffer 9 is stored in a first memory group 6 as a memory address 12, and the output of the buffer 10 is stored in a second memory group 7 as the memory address 13. At this time, when a main body using the memory card accesses the memory card, a rapid signal like a clock signal is inputted to the card address 2. Then, the operation current of the buffers 9, 10 depend on the terminal capacity connected to the output buffers. Thus, by dividing the card address and storing them in the memory, the terminal capacity is reduced, and the operation current of the memory card is reduced.