Title:
【発明の名称】半導体受光素子の評価方法
Document Type and Number:
Japanese Patent JP2596023
Kind Code:
B2
Abstract:
PURPOSE:To evaluate linearity of output characteristics of a semiconductor photodetector in the form of a wafer or chip for decreasing manufacturing cost, by obtaining output characteristics of photoelectric current in relation to intensity of incident light to the photodetector from dependency of capacitance on bias voltages and dependency of series resistance on bias voltages and then evaluating linearity thereof. CONSTITUTION:Output characteristics of photoelectric current in relation to intensity of incident light to a semiconductor photodetector are obtained from dependency of capacitance on bias voltage and dependency of series resistance on bias voltage, and linearity of the output characteristics of the semiconductor photodetector thus obtained is evaluated. More particularly, a prober 26 is brought into contact with a p-electrode of one chip in a wafer 21, and a bias voltage is applied between the prober 26 and a substrate stage 22, so that dependency of capacitance on the bias voltage is measured by adding signal current modulated at a frequency of 1MHz and an amplitude voltage of 10mV. The dependency thus obtained is processed by a computer 24 and recorded in a plotter 25. A photodetector presenting little capacitance at a reverse voltage of 1V is found to have good linearity. A photodetector presenting large capacitance is found to have poor linearity.
Inventors:
Shuzo Kagawa
Application Number:
JP30660987A
Publication Date:
April 02, 1997
Filing Date:
December 02, 1987
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L21/66; G01J1/00; G01R31/26; H01L31/10; (IPC1-7): H01L21/66; G01J1/00; G01R31/26; H01L31/10
Domestic Patent References:
| JP5459890A | ||||
| JP50126182A | ||||
| JP5754379A |
Attorney, Agent or Firm:
Teiichi