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Title:
INTERRUPTION FAULT DETECTION SYSTEM
Document Type and Number:
Japanese Patent JPH0715487
Kind Code:
A
Abstract:

PURPOSE: To provide a circuit system suitable for large scale circuit integration for high density mount by making the circuit operation stable and facilitating the operation verification in the interruption fault detection system comprising all logical circuits for the signal interruption between units.

CONSTITUTION: The system is provided with an interrupt discrimination information multiplexer section 11, an interrupt discrimination information extract section 14, an interrupt block count section 15 and a fault information latch section 16. Signal transmission is confirmed for the discrimination of interruption by the interrupt discrimination information multiplexer section 11 and the interrupt discrimination information extract section 14 and the interrupt block count section 15 counts logically a block of data interruption and uses an overflow signal of the counter to provide an output of an interrupt fault alarm as a binary result of '0' or '1' by the fault information latch section 16.


Inventors:
KIMURA ATSUSHI
Application Number:
JP14874893A
Publication Date:
January 17, 1995
Filing Date:
June 21, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L1/00; H04L69/40; (IPC1-7): H04L29/14; H04L1/00
Domestic Patent References:
JPS63292821A1988-11-30
JPS62219829A1987-09-28
Attorney, Agent or Firm:
Yoshiyuki Iwasa