PURPOSE: To correct distortion of a pulse width of a received start-stop synchronizing signal automatically and to receive it normally.

CONSTITUTION: The circuit is provided with an edge detection circuit 3 operated by a sampling pulse being 1/16 equal divisions of a pulse width in 1-bit provided at the transmission of a start-stop synchronizing signal and with a 16-bit shift register 2 to receive a reception signal. A 4-bit counter 4 counts a sampling pulse number for a period of an adjacent edge detection section outputted from the edge detection circuit 3. A 4-bit latch section outputs an inverse of the MSB of the output of the 4-bit counter 4 and it is exclusively ORed with an output of a flip-flop 6 and when the output of the EXOR is logical 1, a shift register controller 5 outputs a bit inverse signal inverting a bit level of a digit by a number when the content of the 4-bit counter 4 is expressed in a decimal number from a digit latching a newest sampling value of the 16-bit shift register 2 to correct the pulse width of the input signal.