PURPOSE: To improve the yield by dividing a tag memory into an (a)-bit memory part for storing the high-order (a) bits of (n) bits of a tag address and a (b)-bit memory part for storing the low-order (b) bits, and providing the single (a)-bit memory part in common to all entries.

CONSTITUTION: The cache memory is constituted by dividing the tag memory 9 into the 17-bit memory part 9a and 3-bit memory part 9b, and the single 17-bit memory part 9a is provided in common to all the entries of a data memory 7. Then the high-order 17 bits of the tag address 1a of data which are cached first are stored in the 17-bit memory part 9a of the tag memory 9 and only data having matching high-order 17 bits of the tag address 1a can be cached thereafter. Consequently, the contents of the 17-bit memory 9a are fixed to the high-order 17 bits unless all the data in the data memory 7 are made ineffective, and data can be cached only when the 17 bits match.