Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP3007187
Kind Code:
B2
Abstract:
PURPOSE:To prevent the effect of power noise caused in the operation of an output buffer from being imposed on other circuit. CONSTITUTION:A high level power supply and a low level power supply are respectively switched to an operating state power supply path 40a and an operating state ground path 42a respectively in the operation of an output buffer by using a load drive P-MOS49 and a load drive N-MOS55. When the output buffer is inoperative, the high level power supply and the low level power supply are respectively switched to an inoperating state power supply path 41a and an inoperating state ground path 43a by using a load drive P-MOS59 and a load drive N-MOS63.
Inventors:
Harumi Kawano
Application Number:
JP16192391A
Publication Date:
February 07, 2000
Filing Date:
July 03, 1991
Export Citation:
Assignee:
Oki Micro Design Co., Ltd.
Oki Electric Industry Co., Ltd.
Oki Electric Industry Co., Ltd.
International Classes:
G11C11/413; H03K17/16; H03K19/00; H03K19/003; (IPC1-7): H03K19/003; G11C11/413; H03K17/16; H03K19/00
Domestic Patent References:
| JP3143019A | ||||
| JP59224922A | ||||
| JP62210725A | ||||
| JP338639U |
Attorney, Agent or Firm:
Yasunari Kakimoto