Title:
【発明の名称】走査回路
Document Type and Number:
Japanese Patent JP2587546
Kind Code:
B2
Abstract:
A scanning circuit for successively scanning a plural number of capacitive loads comprising: a delay circuit 101 for delaying a supplied pulse signal from a previous stage in accordance with a first clock signal; a switching transistor 102 which is controlled by the first clock signal; an EXNOR circuit 103 which judges whether or not the signal generated by the delay circuit 101 is correct; a non-inverting buffer circuit 104 for reserve of the delay circuit 101; switching transistors 105 and 106 which are controlled in accordance with the signal generated by the EXNOR circuit 103; and an output buffer circuit 107 which is controlled in accordance with the first clock signal or a second clock signal. Accordingly, the scanning circuit can operate correctly even if one of the delay circuit 101 or the non-inverting buffer circuit 104 fails.
Inventors:
ASADA HIDEKI
Application Number:
JP8349991A
Publication Date:
March 05, 1997
Filing Date:
March 22, 1991
Export Citation:
Assignee:
GTC KK
International Classes:
G02F1/133; G09G3/20; G09G3/36; G11C19/00; (IPC1-7): G09G3/36; G02F1/133; G09G3/20
Attorney, Agent or Firm:
Masatake Shiga (2 outside)