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Patent Searching and Data


Title:
TESTING METHOD FOR INPUT/OUTPUT DEVICE IN COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPH0581151
Kind Code:
A
Abstract:

PURPOSE: To shorten the testing time by using an input/output instruction by a group device address.

CONSTITUTION: A central processing unit CPU 1 is provided with the input/ output instruction by the group device address exclusively used for a test. By issuing the input/output instruction by the group device address, all the input/ output devices are made to perform the input/output operations at the same time. At the time of detecting that all the input/output operations are terminated in a channel device CHP, the input/output termination interruption by the group device address is made to generate for the central processing unit CPU 1. When an error is recognized with the input/output termination interruption by the group device address in the central processing unit CPU 1, a sense command by the group device address is issued. After the input/output device in which the error generated is recognized, the detail information of the error is obtained by issuing a normal sense command to the input/output device in which the error generated.


Inventors:
TANAKA NAOHARU
Application Number:
JP24204991A
Publication Date:
April 02, 1993
Filing Date:
September 20, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/22; G06F13/00; (IPC1-7): G06F11/22; G06F13/00
Attorney, Agent or Firm:
Teiichi