Title:
【発明の名称】半導体集積回路およびその製造方法
Document Type and Number:
Japanese Patent JP2519837
Kind Code:
B2
Abstract:
A semiconductor integrated circuit device and its manufacturing method are disclosed, the method comprising the steps of forming, over a semiconductor substrate, a first interconnection layer which involves a step-like surface, forming, over a first interconnection layer, an insulating layer and planarizing the surface of the second insulating layer, providing a plurality of via holes of different depths in the insulating layer reaching the first interconnection layer, subsequent to the step, implanting an impurity ion in the first interconnection layer such that an electronegativity in the first interconnection layer varies in accordance with the depths of the via holes, depositing a metal film in the via holes, and forming a second interconnection layer over the insulating layer so as to be connected to the first interconnection layer by the deposited metal film in the via holes.
Inventors:
SHIBATA HIDEKI
Application Number:
JP1658591A
Publication Date:
July 31, 1996
Filing Date:
February 07, 1991
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/265; H01L21/3205; H01L21/768; H01L23/52; H01L23/522; (IPC1-7): H01L21/768; H01L21/265; H01L21/3205
Attorney, Agent or Firm:
Takehiko Suzue