PURPOSE: To allow an access space during program implementation to be discriminated externally in the irreducible minimum number of bits by outputting a part of address data to the outside of a chip.
CONSTITUTION: Upon the receipt of a request of bus access from an instruction implementation section 106, an access control circuit 108 validates any of a built-in ROM selection signal 115, a built-in RAM selection signal 116 and an external valid signal 117 based on high- -"order 2-bits (space identifier) in address bits and a mode signal latched in a mode signal register 111 to select the access to a built-in ROM 103, a built-in RAM 104 or the outside of a chip. Then an external bus I/F 105 outputs the high-order 2-bit space identifier 120 in a generated address 32 of a CPU 102 inputted from a bus I/F section 107 via an address bus 114 from an output terminal. Thus, a user discriminates to which space a program in implementation accesses based on the 2-bit space identifier 120.
SHIMIZU TORU
IWATA SHUNICHI
MIZUGAKI SHIGEO
NAKAO YUICHI
DOI TOSHIO
